This invention relates to application-specific integrated circuits (“ASICs”), and more particularly to the type of ASICs that are sometimes known as structured ASICs.
Schleicher et al. U.S. patent application Ser. No. 11/097,633, filed Apr. 1, 2005 shows methods for working with a user's logic design to produce data that can be used to produce functionally equivalent implementations of the user's logic design in a programmed field-programmable gate array (“FPGA”) and a structured ASIC. (The Schleicher et al. reference is hereby incorporated by reference herein in its entirety.) For example, in the case of an FPGA, the Schleicher et al. reference shows a succession of steps for manipulating the user's logic design to produce data for use in programming the FPGA to implement that logic design. In the case of a structured ASIC, the Schleicher et al. reference shows a succession of steps for manipulating the user's logic design to produce what the reference calls handoff design files. These are design files that are intended to closely specify how the user's logic design will be actually implemented in a structured ASIC in order to help ensure functional equivalence of this implementation with an FPGA implementation of the same user's logic design. It is recognized, however, that additional work needs to be done on these handoff design files in order to turn them into the final data needed to control production of the structured ASIC. This additional work, referred to in the Schleicher et al. reference as the back end of the structured ASIC design process, is the subject of this invention. Again, as in the Schleicher et al. reference, important goals of this invention are (1) preservation of highly reliable functional equivalence between the resulting structured ASIC and an FPGA implementing the same user's logic design, (2) efficient use of the resources of the structured ASIC, and (3) rapid completion of back end task to facilitate prompt availability of the finished structured ASIC product.